5G infrastructure needs programmability: Page 3 of 4

February 11, 2019 // By Alok Sanghavi, Achronix Semiconductor Corp.
Alok Sanghavi surveys the 5G infrastructure landscape and makes the case for FPGAs and chiplet packaging to support evolving standards and high performance computation.

Discrete architecture cuts time-to-market

The next illustration (Figure 2 below) maps the required processing elements for 5G onto a discrete implementation with separate devices for CPU SoC, look-aside FPGA acceleration and antenna interfacing. This configuration reflects implementation that could deploy in 5G prototyping and early-production, before optimized 5G ASICs are available.

CPU system-on-chip includes, for example, an ARM processing complex as well as DSP cores for Layer-1 processing and hardened accelerators, for fixed, well-defined functionality. In this example, it is assumed that an existing 4G ASIC SoC is available and therefore has general purpose acceleration (e.g. MACSEC) as well as LTE specific acceleration: Forward Error Correction (specifically turbo codec), Fast Fourier Transform, and Discrete Fourier Transform to support SC-FDMA on the uplink.

Flexible Antenna Interface - As described earlier, the fronthaul antenna interface is well suited to an FPGA implementation. This is configured in-line, with the data flowing from the Radio Unit (on the uplink) and then the protocol being converted to something with standard connectivity like Ethernet.

Hardware Acceleration FPGA - A look-aside acceleration FPGA implements all necessary computationally-intensive functions that are unavailable on the base SoC. This can be 5G specific functions or those previously not envisioned.

In the example shown here, a CCIX interconnect is used. The standard allows processors based on different instruction set architectures to extend the benefits of cache coherent, peer processing to a number of acceleration devices including FPGAs and custom ASICs.


Figure 2: Discrete archtecture for 5G time-to-market solution


The Chiplet Alternative

Figure 3 shows a comparable architecture as that shown in Figure 2 but reconfigured with a chiplet based approach. In this case, a higher bandwidth, lower latency and lower power interface is used to connect the CPU SoC die with a look-aside hardware acceleration FPGA chiplet. The FPGA device supporting the fronthaul connection to the Radio Unit is not package integrated in this example but could be; indeed, it could be the same device chiplet as the hardware acceleration chiplet, if there are sufficient resources.

Figure 3: Chiplet-based approach for greater integration

The two primary techniques for package integration are with a silicon interposer or with an organic substrate and some form of Ultra-Short Reach (USR) transceiver.

Next: 5G vision

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